1. Field of the Invention
This invention relates generally to a circuit module for utilizing a number of programmable logic devices (PLDs), and specifically in the area of reconfigurable high speed communication protocol processing.
2. Description of Related Art
A programmable logic device (PLD) is an integrated circuit device with configurable logic, flip-flops and/or RAM linked together with programmable interconnect. Most PLDs are arranged so that data flows most efficiently either along a plurality of parallel rows or a plurality of parallel columns transverse to the rows. The logic is defined by programming the interconnect using RAM, ROM, EEPROM or fusable links. Though various devices use different architectures, all are based on this fundamental idea.
Present PLD devices do not have the wide data path or large number of programmable gates needed for many aggressive applications. Currently available reconfigurable logic circuit cards are targeted for reconfigurable computing applications rather than reconfigurable high-speed communications protocol processing. None of these currently available products has a large gate count in few logic devices. Nor do these currently available products incorporate infinitely extensible clocking to multiple boards. The processing of communication protocols in general purpose computing hardware is difficult to scale to 10 to 100 Gigabit/second (Gb/s) throughputs, due to individual bit operations that typically require many instruction cycles per data unit processed. Therefore, it is necessary to provide wide high speed parallel processing in excess of 400 bits. Also, basic logic devices are expandable as ever higher density devices become available.
An application specific integrated circuit (ASIC) is a custom chip designed for a specific application. It is designed by integrating standard cells from a library. ASIC design is faster than designing a chip from scratch, and design changes can be made more easily. The current crop of digital emulators used in the development of CMOS ASICs are expensive (&gt;$100K) and generally limited to a specific set of devices.
The representative cross section of available reconfigurable logic board products fall into the following categories: 1) small gate count, low cost boards; 2) small gate count, moderately expandable boards; 3) medium gate count, highly flexible on-board interconnect boards; 4) large gate count boards intended for reconfigurable computing applications; and 5) large gate count boards with wide data paths suitable for reconfigurable communication protocol processing applications. The state of the art in marketed reconfigurable logic circuit boards in each of the aforementioned categories are represented by: 1) Associated Professional Systems, APS-L84 (20,000 gates, $850); 2) Virtual Computer Corp., EVC1 (20,000 gates, limited expandability); 3) APTIX, MP4 (estimated 300,000 gates); 4) Virtual Computer Corp., P-Series Reconfigurable computers (1.04 million gates; 0.8 million gates in virtual processing array); and 5) the present invention (1.1 million gates, 384 bit wide data path).
The APS-L84 made by Associated Professional Systems uses a Lucent 2C15A PLD device. This product has comparatively narrow data paths (80 bits) and no expansion capability. Its gate count is 20,000. It utilizes an ISA interface. The APS-L84 is incapable of high speed operation.
Virtual Computer Corporation's EVC1 utilizes a Xilinx 4020 PLD device. The EVC1 has 96 bit wide data paths and limited expansion capability. Additionally, the components on the board are only capable of operation as high as 50 MHz; the current invention is capable of operation as high as 100 MHz. The EVC1 uses a SBus as its interface.
Although it has an estimated 300,000 gates in conjunction with 160 bit wide data paths, the APTIX MP4 is still incapable of high speed operation. The Lucent, Xilinx and Altera PLD devices used by the MP4 are only capable of operation as high as 50 MHz. It has limited expansion capability and no interface.
One related product is the P-Series VIRTUAL COMPUTER.TM. (P4) made by Virtual Computer Corporation. Even though this product has much narrower data paths (32 bits) and limited expansion capability (32 boards), it is the only one with a sizable number of gates (1.04 million gates). The P4 board uses SRAM based PLD technology but at greatly reduced chip complexity (Xilinx 4020 only contains 2,000 gates). This allows for far greater complexity logic blocks without the difficulty of partitioning the design into small logic blocks. The P4 can be expanded to only 32 boards operating in parallel. The P4 board does not appear to have a way of storing its configuration (no PROMs). It appears that the PSVC must be connected to a SBus (SUN Workstation) or similar host to operate. The P4 uses I-Cube IQ-160's for connection between PLDs. The IQ-160 is a switch matrix crossbar with 160 I/O pins. The bus between parts is limited to 32 bits and 4 virtual channels. The observability of the P4 buses is reduced since there is no apparent way to debug the P4 other than by using scan bits. Access to the internal buses of the P4 is limited.